The invention relates to a method and apparatus for controlling a video data memory in a time base corrector to effect color correction and, more particularly, to changing the read timing of a given data memory by a fraction of the read/write cycle without affecting the write timing, and vice versa.
In the usual architecture of a digital data memory and its associated memory control logic, as typified by a random access memory operating at a selected data rate, data is written into the memory at a rate determined by the incoming data clock, and is read from the memory at a rate determined by a read clock, generally operating at some reference frequency. The read and write portions of the memory cycle generally are interlaced and interlocked so as to provide a selected synchronization between the writing and reading processes. However, there are situations where the read or write cycles may be asynchronous to allow the selective delay of incoming or outgoing data. In these situations, the delay time is changed by an integer number of the memory cycles corresponding to the relationship selected between write and read addresses. That is, present data memories and their associated control logic are not capable of changing, (i.e., shifting or delaying) the read timing or write timing relative to each other by a fraction of the read/write cycle. However, it is disadvantageous in some fields to not be able to unlock the read/write timing, that is, to not be able to delay, for example, the read timing relative to the write timing by a fraction of the read/write cycle. This disadvantage is exemplified in the field of time base correction of video signals.
Thus, by way of example only, in a video tape recording system (VTR), a time base corrector (TBC) generally is employed to compensate for distortions of the time base of the off-tape video signal by means of a variable delay. In presently known time base correctors the variable delay is accomplished by employing a digital memory to store data representing the input video signal and to enable readout with proper phase relative to a reference signal.
Conventionally, the video signal is sampled at a rate that is too high for those semiconductors which are economically feasible for use in VTR systems. In order to slow down the data rate to just below the semiconductor's speed, the samples of the video signal are first collected in pairs and later, before storage in the main memory of TBC, in blocks consisting of a number of pairs. The pairs are processed at twice the color subcarrier frequency. The rate of writing and reading the data blocks is dictated by the speed of the memory chips, which may be 250 nanoseconds for example. A single block may be as large as 5 or 6 pairs, the total of 90 or 108 bits wide. Each block is stored at a single address in the digital video memory. For each memory cycle, one block of video data is written in and one block is read out of the memory in an interlaced read/write manner. After readout from the memory the blocks are disassembled into pairs.
The relationship (usually called color sequence) between vertical synchronizing pulses, horizontal synchronizing (sync) pulses, and color burst in a color video signal according to the NTSC standard results in a sequence of four different fields (two different color frames) consisting of two different types of lines. The relationship in PAL color video signal results in an eight field sequence and four different types of lines. The different types of lines may be represented within TV equipment by an H/2 signal in NTSC color television standard, and by H/4 and H/2 signals in PAL and PAL-M standards.
In a VTR record-reproduce process, and in still frame or slow motion playback in particular, the color sequence may become distorted and needs to be regenerated by time base correction. In this process the sync generator, which may be a part of the TBC system, signals which line type is required at any given moment of time. Generally, in prior art time base correction systems of a VTR, the proper relationship of vertical and horizontal sync with respect to each other and with respect to the other video signals in the TV studio is restored by means of a variable delay. The proper relationship between horizontal sync and color burst is restored by using proper filtering for separating luminance and chrominance components of the video signal and by demodulating the color subcarrier down to color modulating components, which are then used to modulate a new subcarrier having a standard relationship to horizontal sync. However, with this approach, degradation of picture quality is known to occur.
Therefore, it would be desirable to make the correction by shifting the active video portion of the composite video signal horizontally by the required fraction of the subcarrier cycle or vertically by a horizontal line, or by a combination of both, with respect to the sync and burst portions of the video signal. However, in presently known time base correctors which incorporate a digital memory as means of variable delay, as previously mentioned, it is not possible to shift the video data at the output of the memory by a fraction of the memory read/write cycle without disturbance of the write function of the memory, because the write and read portions of the memory cycle are interlaced and interlocked. It is only possible to shift in increments of one block and thus the delay time cannot be changed by the exact amount needed.
Accordingly, in a TBC system in particular, in some modes of operation it would be a distinct advantage to provide color correction by shifting the color signal horizontally by the required fraction of the subcarrier cycle. Further, in audio or video data memories wherein digital or analog signals are being processed, there are situations where it would be a distinct advantage to be able to control the timing of the read process relative to the write process, i.e., to unlock the read/write groups controlling the data memory and shift the read or write timing by a fraction of the read/write cycle.
The invention provides the advantages of previous mention by providing a data memory control circuit wherein the interlaced write and read portions of a memory cycle are suitably selected (for example condensed) in time to provide enough free time space within a memory cycle to enable shifting of the write or read portion independently of the read or write portion respectively. In a TBC system this allows correction of the color sequence of a video signal by shifting the color signal horizontally by the required fraction of the subcarrier cycle.
According to the invention, groups of write pulses and read pulses are formed by common circuitry. The timing relationship between the write and read groups is determined by the relationship between pulses which trigger the generation of each group. By way of example, in a time base corrector system, the read group trigger pulse is shifted with respect to a time base correction reference by an amount required for color sequence correction, within available free time limits of the memory cycle. The shift of the read trigger pulse results in a corresponding shift of the read group pulses, and a resulting shift of the data output from the video data memory and the active video portion of the video signal relative to the time base corrector output sync and burst signals. That is, although the read and write portions are still interlaced, they no longer are interlocked which allows shifting the read portion within available time space within the read/write cycle with the resulting attendant shift in the data output for purposes of color correction.
As previously mentioned, the invention is equally applicable in data memories other than those used in the time base correction process of previous mention, and for purposes other than color correction in video signal processing, as is further understood by the description below in the specification.